The background description provided herein is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Semiconductor memory may be classified as non-volatile memory or volatile memory. A non-volatile memory, e.g., NAND flash memory, may store and retain information even when the non-volatile memory is not connected to a power source. NAND flash memory, or simply NAND memory, or a NAND memory system, may be included in a storage device to store data. Bits may be stored into cells, or memory cells, of a NAND memory, which may be made of floating-gate transistors. Multi-level NAND memory may store multiple bits of data per cell, and may include three level cells (TLC) that store three bits of data per cell, quad level cells (QLC) that store four bits of data per cell, and other types of cells such as multi-level cells (MLC) that store two bits of data per cell. TLC and QLC NAND is typically programmed with more than one pass. In a NAND device, several non-idealities may result in an increased raw bit error rate (RBER). One of these non-idealities is temperature dependence of the NAND cells (e.g., when reading cells at a temperature different than the temperature during programming the cells, the threshold voltage of the cells may appear lower or higher than the threshold voltage if the cells are read at the same temperature.) As an example, an internal pre-read of eight threshold voltage (VT) states during a third pass of a 2-8-16 technique may occur at different temperature conditions than when the states were programmed during the second pass. This may cause a high RBER and potential misplacements of sixteen VT states, which may lead to fatal errors that may be uncorrectable by an external error correcting code (ECC) engine on system platforms.